This invention relates to an image processing apparatus being connected to a host computer and an external machine such as a copier, a scanner, or a printer for writing image data from the host computer or external machine into a memory of the image processing apparatus and outputting the once written data to the host computer or external machine.
In recent years, a system has been constructed wherein an engineering subsystem (ESS) is connected between a host computer and an external machine such as a copier, a scanner, or a printer for outputting a computer graphics image, etc., prepared by the host computer to the copier, printer, etc., and outputting image data read through the scanner, copier, etc., to a CRT of the host computer. If a network like a LAN (local area network) is used, a number of external machines can be connected and a wide area system can be constructed.
To output image data transferred from the host computer to the external machine such as a copier or printer in such a system, a process of writing the image data transferred from the host computer into an image memory in the ESS, then reading the image data from the image memory and transferring the image data to a predetermined external machine is required.
To output image data read through the scanner, copier, etc., to the CRT of the host computer, a process of writing the image data read through the scanner, copier, etc., into the image memory in the ESS, then reading the image data from the image memory and transferring the image data to the host computer is required.
The conventional system having the function as described above cannot output an image transferred from the host computer, for example, to a number of external machines at the same time. Thus, to output the same image data to a number of external machines, a process of writing the image data transferred from the host computer into the image memory in the ESS, then reading the image data from the image memory and transferring the image data to a predetermined external machine must be repeated more than once; long time is required.
Further, for example, in a conventional system having an image memory into which A3-size image data can be written, to transfer A4-size image data from the host computer, write the image data into the image memory, and output the written image data into a copier, when image data as large as the A4 size is read from the image memory, the remaining A4-size image memory area cannot be accessed. Thus, the memory use efficiency lowers. To perform such print operation consecutively, all the image data as large as the A4 size is read out before writing the image data transferred from the host computer is started. Thus, the print operation throughput lowers.
As means to avoid lowering the memory use efficiency or operation throughput, a memory may be divided into parts which can be operated independently. Such means is described in the Unexamined Japanese Patent Application Publication No. Hei 2137040, the Examined Japanese Patent Application Publication No. Hei 6-93244, etc., for example.
In the system described in the Unexamined Japanese Patent Application Publication No. Hei 2-137040, an address generated from an address generator is supplied to an image memory, a specific one bit of the address is used as a chip enable signal of the image memory, and image memory divisions can be operated independently. However, the chip enable signal, which is a specific address bit, is exclusive, thus the image memory divisions cannot be accessed at the same time. The system described in the Examined Japanese Patent Application Publication No. Hei 6-93244 uses two memories in a pair and when the output enable signal for one memory is active, the output enable signal for the other memory becomes inactive. This means that when one memory performs write operation, the other memory performs read operation. However, in such a configuration, data written into the memory cannot be output to a number of external machines at the same time.